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«Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 Server Architecture Oracle White Paper—Oracle's Sun SPARC ...»

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Optional XAUI adapter cards required for access to dual 10 GbE ports on all systems. Each XAUI consumes a PCIe slot.

Eight-disk backplane is not supported with 1.6 GHz CPU (Oracle's Sun SPARC Enterprise T5120 server) or with 1.4 GHz CPU or DC power supply (Oracle's Sun SPARC Enterprise T5140 server).

Leading Reliability, Availability, and Serviceability The Oracle Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 servers provide excellent reliability, availability, and serviceability (RAS) characteristics. Highly reliable parts and a relatively low total component count minimize the opportunity for system errors. Dual PCIe root complexes and the ability to configure multiple processors on Oracle's Sun SPARC Enterprise T5140/T5240 servers add to resiliency. In addition, these servers include core and thread off-lining capabilities, integrated disk RAID Optional XAUI adapter cards required for access to dual 10 GbE ports on all systems. Each XAUI consumes a PCIe slot.

Eight-disk backplane is not supported with 1.6 GHz CPU (Oracle's Sun SPARC Enterprise T5120 server) or with 1.4 GHz CPU or DC power supply (Oracle's Sun SPARC Enterprise T5140 server).

Eight-disk backplane is not supported with 1.6 GHz CPU (Oracle's Sun SPARC Enterprise T5120 server) or with 1.4 GHz CPU or DC power supply (Oracle's Sun SPARC Enterprise T5140 server).

Using an XAUI adapter card converts one RJ-45 Gigabit Ethernet port into a 10 GbE port. If two XAUI ports are used, only 2 GbE ports are available.

Optional XAUI adapter cards required for access to dual 10 GbE ports on all systems. Each XAUI consumes a PCIe slot.

Oracle White Paper—Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 Server Architecture functions, and extensive ECC hardware protection—along with redundant hot-swap disks, power supplies, and fans. The following key design elements in the Oracle Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 servers are key to improving

the dependability of IT services:

Reduced parts count  Processor thread and core off-lining and built-in RAID capabilities  Redundancy and hot-swap components  Parity protection and error correction capabilities  System monitoring  Integrated Lights Out Manager service processor  Superior energy efficiency  Robust virtualization technology  Comprehensive fault management  Innovative Support for Solid State Drives Modern servers are driving throughput levels that can rapidly outpace the capabilities of traditional storage solutions. While many servers can achieve processing capabilities in excess of one million I/O operations per second (IOPS), today’s fastest hard disk drives (HDDs) are only capable of about 300 to 400 IOPS. To match throughput more closely to server performance, and to address the challenging demands of data-intensive applications, many data centers implement large pools of high-speed disk drives. In some cases, a large buffer of expensive DRAM is also deployed so that the application’s working set can be stored in memory to reduce latency.

Flash technology provides a more-economical alternative that can dramatically enhance application I/O performance while also operating with significantly better energy efficiency than conventional HDDs. Recent advances in the quality of flash technology have made solidstate drives (SSDs) an effective and reliable solution for enterprise storage. Flash technology contains no moving parts, avoiding the seek times and rotational latencies inherent with traditional HDD technology.

Because SSDs offer low latency and are less expensive than DRAM storage, they balance cost and performance in a manner that can provide significant value for I/O-intensive workloads.

SSDs offer a disk drive form factor (Figure 3), and are directly supported by the drive bays of Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 servers.

Oracle White Paper—Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 Server Architecture Figure 3. SSDs provide enterprise flash technology in a standard disk drive form factor.

Space, Watts, and Performance: The SWaP Metric Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 servers deliver leading performance across a range of multithreaded workloads and benchmarks. However, with energy and real estate costs and pressures, it is not enough to measure performance in isolation. Delivering the required level of throughput in a fixed space and power envelope is critical. Traditional system-to-system benchmarks are valuable as a way of comparing one system to another, but are limited when it comes to understanding the power and density attributes of the systems being compared. For this reason, Oracle has developed the SWaP metric, standing for space, watts, and performance.

Designed to provide a simple and transparent measure of overall server efficiency, SWaP is

calculated using the following formula:

SWaP = Performance / (Space * Power Consumption) where, Performance is measured by industry-standard benchmarks  Space refers to the height of the server in rack units  Power is measured by watts used by the system, taken during actual benchmark runs or from  vendors’ site planning guides UltraSPARC T2 and T2 Plus Processors The UltraSPARC T2 and UltraSPARC T2 Plus processors are the industry’s first systems-on-achip, supplying the most cores and threads of any general-purpose processors available, and integrating all key system functions.





The World's First Massively Threaded Systems-on-a-Chip Oracle White Paper—Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 Server Architecture The UltraSPARC T2 and UltraSPARC T2 Plus processors eliminate the need for expensive custom hardware and software development by integrating computing, security, and I/O onto a single chip. Binary compatible with earlier UltraSPARC processors, no other processor delivers so much performance in so little space and with such small power requirements— letting organizations rapidly scale the delivery of new network services with maximum efficiency and predictability. The UltraSPARC T2 Plus and UltraSPARC T2 processors are shown in Figure 4, to the left of the previous-generation UltraSPARC T1 processor. Even with twice the computational throughput and significantly higher levels of integration, the UltraSPARC T2 and UltraSPARC T2 Plus processors are physically smaller than the UltraSPARC T1 processor.

Figure 4. The UltraSPARC T2 Plus, UltraSPARC T2, and UltraSPARC T1 processors with CoolThreads technology (left to right respectively) allow organizations to rapidly scale the delivery of new network services with maximum efficiency and predictability.

Table 2 provides a comparison between the UltraSPARC T2 and the UltraSPARC T1 processor.

TABLE 2. ULTRASPARC T1, ULTRASPARC T1T2, AND ULTRASPARC T1T2 PLUS PROCESSOR FEATURES

–  –  –

A. Two-socket implementations include Oracle's Sun SPARC Enterprise T5140/T5240 servers, whereas Oracle's Sun SPARC Enterprise T5440 server represents a four-socket implementation.

Taking Chip Multithreaded Design to the Next Level When designing the next-generation of CMT processors, the in-house design team started

with key goals in mind:

Increasing computational capabilities to meet the growing demand from Web applications by  providing twice the throughput of the UltraSPARC T1 processor Supporting larger and more-diverse workloads with greater floating-point performance  Oracle White Paper—Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 Server Architecture Powering faster networking to serve new network-intensive content  Providing end-to-end data center encryption  Increasing service levels and reducing downtime  Improving data center capacities while reducing costs  CMT architecture is ultimately very flexible, allowing different modular combinations of processors, cores, and integrated components. The considerations listed above drove an internal engineering effort that compared different approaches with regard to making improvements on the successful UltraSPARC T1 architecture. For example, simply increasing the number of cores would have gained additional throughput, but would have resulted in consuming extra die area, leaving no room for integrated components such as floating-point processors.

The final UltraSPARC T2 and UltraSPARC T2 Plus processor designs recognize that memory latency is truly the bottleneck to improving performance. By increasing the number of threads supported by each core, and by further increasing network bandwidth, these processors are able to provide approximately twice the throughput of the UltraSPARC T1 processor.

Oracle White Paper—Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 Server Architecture Figure 5. A single eight-core UltraSPARC T2 or UltraSPARC T2 Plus processor supports up to 64 threads, with up to 2 threads running in each core simultaneously.

Each UltraSPARC T2 and UltraSPARC T2 Plus processor provides up to eight cores, with each core able to switch between up to eight threads (64 threads per processor). In addition, each core provides two integer execution units, so that a single UltraSPARC core is capable of executing two threads at a time. Figure 5 provides a simplified high-level illustration of the thread model supported by an eight-core UltraSPARC T2 or UltraSPARC T2 Plus processor.

UltraSPARC T2 and UltraSPARC T2 Plus Processor Architecture The UltraSPARC T2 processor and the UltraSPARC T2 Plus processor extend Oracle’s CMT initiative with an elegant and robust architecture that delivers real performance to applications.

Oracle White Paper—Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 Server Architecture UltraSPARC T2 Processor Architecture A high-level block diagram of the UltraSPARC T2 processor is shown in Figure 6.

Figure 6. The UltraSPARC T2 processor combines up to eight cores, memory management, cryptographic support, 10 GbE, and PCIe on a single chip.

Oracle's Sun SPARC Enterprise does not expose 10 GbE interfaces.) Up to eight cores on each UltraSPARC T2 processor are interconnected with a full on-chip nonblocking 8 x 9 crossbar switch. The crossbar connects each core to the eight banks of Level 2 cache, and to the system interface unit for IO. The crossbar provides approximately 300 GB/sec of bandwidth and supports 8-byte writes from a core to a bank and 16-byte reads from a bank to a core. The system interface unit connects networking and I/O directly to memory through the individual cache banks. Using FB-DIMM memory supports dedicated northbound and southbound lanes to and from the caches to accelerate performance and reduce latency. This approach provides higher bandwidth than with DDR2 memory, with up to 42.4 GB/sec of read bandwidth and 21 GB/sec of write bandwidth.

Each core provides its own fully pipelined floating point and graphics unit (FPU), as well as a stream processing unit (SPU). The FPUs greatly enhance floating-point performance over that of the UltraSPARC T1 processor, while the SPUs provide wire speed cryptographic acceleration with more than 10 popular ciphers supported, including DES, 3DES, AES, RC4, SHA-1, SHAMD5, RSA to 2048 key, ECC, and CRC32. Embedding hardware cryptographic acceleration for these ciphers allows end-to-end encryption with no penalty in either performance or cost.

Oracle White Paper—Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 Server Architecture UltraSPARC T2 Plus Processor Architecture Figure 7 provides a block-level diagram of the UltraSPARC T2 Plus processor.

Figure 7. The UltraSPARC T2 Plus processor provides four coherence links to connect to up to four other processors.

The UltraSPARC T2 Plus architecture omits the dual on-chip 10 GbE interfaces that are provided on the UltraSPARC T2 processor, and uses the on-chip real estate to provide four coherency units (CUs). The processor also replaces two memory channels with four coherence channels (or coherence links)—one provided by each CU. These links run a cache coherence (snoopy) protocol over an FB-DIMMlike physical interface to provide up to 4.8 gigatransfers per port, providing 204 Gb/sec in each direction. The memory link speed of the UltraSPARC T2 Plus processor was also increased to 4.8 Gb/sec over the 4.0 Gb/sec of the UltraSPARC T2 processor.

The UltraSPARC T2 Plus processor can support both two- and four-socket implementations.

A typical two-socket implementation is shown in Figure 8. Dual-socket UltraSPARC T2 Plus implementations interconnect the processors’ four coherence links; no additional circuitry is required.

Oracle White Paper—Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 Server Architecture Figure 8. This is a typical dual-socket UltraSPARC T2 Plus configuration.

Core Architecture and Pipelines Both the UltraSPARC T2 and UltraSPARC T2 Plus processors share the same core design.

Figure 9 provides a block-level diagram representing a single UltraSPARC core on the UltraSPARC T2 processor (up to eight cores are supported per processor).

Figure 9.This is a block-level diagram of the UltraSPARC T2 and UltraSPARC T2 Plus core.

Oracle White Paper—Oracle's Sun SPARC Enterprise T5120/T5220 and Oracle's Sun SPARC Enterprise T5140/T5240 Server Architecture Components implemented in each core include Trap logic unit. The trap logic unit (TLU) updates the machine state as well as handling  exceptions and interrupts.

Instruction fetch unit. The instruction fetch unit (IFU) includes the 16 KB instruction cache  (32-byte lines, 8-way set associative) and a 64-entry fully associative instruction translation lookup buffer (ITLB).

Integer execution unit. Dual integer execution units (EXUs) are provided per core with four  threads sharing each unit. Eight register windows are provided per thread, with 160 integer register file (IRF) entries per thread.



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